The present invention relates to the organization, construction and sequencing of associative processors embodying a fully parallel associative memory. An associative memory is a device wherein stored data words are identified according to their contents, hence it is sometimes called a content addressable memory. Such a memory is to be distinguished from the more widely used coordinate addressable memories, such as the Random Access Memory (RAM), in which stored data are accessed by their location or address. An associative memory accepts as input a comparand (or operand) word and a mask word, searches all stored data locations simultaneously for a match between the unmasked bits of the comparand and all the stored words, and identifies matching data words by setting a marker or tag in a TAG register.
Processors using associative memory were expected to be particularly effective in the solution of complex problems, such as image and radar-data processing, which require many involved operations on a large body of data, achieving their effectiveness and high speed by virtue of parallel operation on all data locations simultaneously. However, associative processors never realized their full potential partly because their associative memory was not implemented as a fully parallel, high density, integrated device, but was emulated using standard RAM circuits. Emulaton slowed down memory operation by forcing it to be bit serial and by moving comparison logic off-chip. An even more serious limitation to their speed and effectiveness is the fact that associative processors often operate on a rather small subset of the stored data due to lack of a common operand.